{"id":415584,"date":"2024-10-20T06:06:03","date_gmt":"2024-10-20T06:06:03","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bsi-pd-iec-ts-62607-6-162022\/"},"modified":"2024-10-26T11:20:30","modified_gmt":"2024-10-26T11:20:30","slug":"bsi-pd-iec-ts-62607-6-162022","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bsi-pd-iec-ts-62607-6-162022\/","title":{"rendered":"BSI PD IEC TS 62607-6-16:2022"},"content":{"rendered":"
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2<\/td>\n | undefined <\/td>\n<\/tr>\n | ||||||
4<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
6<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | 1 Scope 2 Normative references 3 Terms and definitions <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 3.1 General terms 3.2 Key control characteristics measured in accordance with this document <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 3.3 Terms related to the measurement method 4 General 4.1 Measurement principle 4.2 Sample preparation method 4.2.1 Sample preparation 4.2.2 Fabrication of FET <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 4.3 Description of measurement equipment Figures Figure 1 \u2013 Schematic of a back-gated graphene FET (inset: top view of the optical microscopic image) <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 4.4 Ambient conditions during measurement Figure 2 \u2013 Experimental setup for measurements of electrical properties of FET device <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | 5 Measurement procedure 5.1 Calibration of measurement equipment 5.2 Detailed protocol of the measurement procedure 6 Data analysis and interpretation of results 6.1 General 6.2 When the minimum conductance neutral point is clear Tables Table 1 \u2013 Specification of key control characteristics, 2D carrier concentration <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 6.3 When the minimum conductance neutral point is unclear 7 Results to be reported 7.1 Cover sheet Figure 3 \u2013 Voltage shift obtained from transfer curves upon plasma doping with various plasma treatments onto the graphene, using 300-nm-thick SiO2 back gate insulator Figure 4 \u2013 Voltage shift obtained from transfer curves of MoS2 FET <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 7.2 Product or sample identification 7.3 Measurement conditions 7.4 Measurement specific information 7.5 Measurement results <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | Annex A (informative)Graphene FET A.1 Background A.2 Test report Table A.1 \u2013 2D carrier concentration measured from graphene-FET for different doping-inducing Ar plasma treatment times <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | Annex B (informative)Graphene\/hBN\/MoS2 heterostructure memory FET B.1 Background Figure B.1 \u2013 Heterostructure FETs: (a) schematic view and circuit diagram of the fabricated device; (b) optical microscopic photograph of GBM FET; (c) optical microscopic photograph of MBG FET <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | Figure B.2 \u2013 Voltage shift obtained from transfer curves of two types of memory device upon charge injection <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | B.2 Test report Table B.1 \u2013 Carrier concentration derived from the electrical characteristics of GBM and MBG <\/td>\n<\/tr>\n | ||||||
21<\/td>\n | Annex C (informative)MoTe2 FET C.1 Background Figure C.1 \u2013 Optical microscopic image of MoTe2 FET and the thickness of 2D MoTe2 measured by AFM <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | C.2 Test report Figure C.2 \u2013 Voltage shift observed from transfer curves measured by using 2D MoTe2 FET <\/td>\n<\/tr>\n | ||||||
23<\/td>\n | Annex D (informative)WSe2 FET D.1 Background Figure D.1 \u2013 WSe2 FET <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | D.2 Test report Figure D.2 \u2013 Transfer curves of 2D WSe2 FET devices before and after doping with contacts (inset: output curves of devices before and after doping) <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Nanomanufacturing. Key control characteristics – Two-dimensional materials. Carrier concentration: Field effect transistor method<\/b><\/p>\n |